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Wireless Components
ASK/FSK Single Conversion Receiver TDA 5220 Version 0.1
Target Specification October 2001
confidential preliminary
confidential Revision History Current Version: 0.1. as of 31.10.01 Please note that this is a target specification that is subject to change. Previous Version: n.a. Page (in previous Version) Page(s) (in current Version) Subjects (major changes since last revision)
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Edition 10.01 Published by Infineon Technologies AG, Balanstrae 73, 81541 Munchen (c) Infineon Technologies AG October 2001. All Rights Reserved. Attention please! As far as patents or other rights of third parties are concerned, liability is only assumed for components, not for applications, processes and circuits implemented within components or assemblies. The information describes the type of component and shall not be considered as assured characteristics. Terms of delivery and rights to change design reserved. Due to technical requirements components may contain dangerous substances. For information on the types in question please contact your nearest Infineon Technologies Office. Infineon Technologies AG is an approved CECC manufacturer. Packing Please use the recycling operators known to you. We can also help you - get in touch with your nearest sales office. By agreement we will take packing material back, if it is sorted. You must bear the costs of transport. For packing material that is returned to us unsorted or which we are not obliged to accept, we shall have to invoice you for any costs incurred. Components used in life-support devices or systems must be expressly authorized for such purpose! Critical components1 of the Infineon Technologies AG, may only be used in life-support devices or systems2 with the express written approval of the Infineon Technologies AG. 1 A critical component is a component used in a life-support device or system whose failure can reasonably be expected to cause the failure of that lifesupport device or system, or to affect its safety or effectiveness of that device or system. 2 Life support devices or systems are intended (a) to be implanted in the human body, or (b) to support and/or maintain and sustain human life. If they fail, it is reasonable to assume that the health of the user may be endangered.
1
2.1 2.2 2.3 2.4
Table of Contents
i
1 Table of Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2 Product Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Application . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Package Outlines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1 2 2 2 3
3 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.1 3.2 3.3 3.4 Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Pin Definition and Function. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Functional Block Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Functional Blocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1 2 3 9 9 9 10 10 11 11 11 12 12 12 12
3.4.1 Low Noise Amplifier (LNA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.4.2 Mixer. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.4.3 PLL Synthesizer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.4.4 Crystal Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.4.5 Limiter. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.4.6 FSK Demodulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.4.7 Data Filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.4.8 Data Slicer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.4.9 Peak Detector. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.4.10 Bandgap Reference Circuitry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.1 4.2 4.3 4.4 4.5 4.6 Choice of LNA Threshold Voltage and Time Constant. . . . . . . . . . . . . . . . . . . . . . . . . . . . Data Filter Design. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Quartz Load Capacitance Calculation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Quartz Frequency Calculation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Data Slicer Threshold Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ASK/FSK Switch Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1 2 4 5 6 7 8 9 10 11
4.6.1 FSK Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.6.2 ASK Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.7 Principle of the Precharge Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5 Reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.1 Electrical Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1 2 3 4 9
5.1.2 Operating Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.1.3 AC/DC Characteristics at TAMB = 25C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.1.4 AC/DC Characteristics at TAMB = -40 to 105C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
TDA 5220
preliminary
confidential
Product Info
Product Info
General Description The IC is a very low power consump- Package tion single chip FSK/ASK Superheterodyne Receiver (SHR) for the frequency bands 810 to 870 MHz and 400 to 440 MHz. The IC offers a high level of integration and needs only a few external components. The device contains a low noise amplifier (LNA), a double balanced mixer, a fully integrated VCO, a PLL synthesiser, a crystal oscillator, a limiter with RSSI generator, a PLL FSK demodulator, a data filter, a data comparator (slicer) and a peak detector. Additionally there is a power down feature to save battery life.
s
Features
Low supply current (typ. at 868MHz Is = 5.9mA in FSK mode, Is = 5.2mA in ASK mode) Supply voltage range 5V 10% Power down mode with very low supply current (50nA typ) FSK and ASK demodulation capability Fully integrated VCO and PLL Synthesiser ASK sensitivity < -107dBm Keyless Entry Systems Remote Control Systems
s
Selectable frequency ranges 810870 MHz and 400-440 MHz Limiter with RSSI generation, operating at 10.7MHz Selectable reference frequency 2nd order low pass data filter with external capacitors Data slicer with self-adjusting threshold FSK sensitivity <-100dBm
s
s s
s s
s
s
s
s
s
Application
s s
s s
Alarm Systems Low Bitrate Communication Systems
Ordering Information
Type TDA 5220 samples available on tape and reel Ordering Code Package P-TSSOP-28-1
Wireless Components
Product Info
Target Specification, October 2001
2
Product Description
Contents of this Chapter 2.1 2.2 2.3 2.4 Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-2 Application . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-2 Package Outlines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-3
TDA 5220
preliminary
confidential
Product Description
2.1 Overview
The IC is a very low power consumption single chip FSK/ASK Superheterodyne Receiver (SHR) for the frequency bands 810 to 870 MHz and 400 to 440 MHz. The IC offers a high level of integration and needs only a few external components. The device contains a low noise amplifier (LNA), a double balanced mixer, a fully integrated VCO, a PLL synthesiser, a crystal oscillator, a limiter with RSSI generator, a PLL FSK demodulator, a data filter, a data comparator (slicer) and a peak detector. Additionally there is a power down feature to save battery life.
2.2 Application
s s s s
Keyless Entry Systems Remote Control Systems Alarm Systems Low Bitrate Communication Systems
2.3 Features
s
Low supply current (at 868MHz Is = 5.9 mA typ. FSK mode, 5.2mA typ. ASK mode) Supply voltage range 5V 10% Power down mode with very low supply current (50nA typ) FSK and ASK demodulation capability Fully integrated VCO and PLL Synthesiser RF input sensitivity ASK < -107dBm RF input sensitivity FSK < -100dBm Selectable frequency ranges 810-870 MHz and 400-440 MHz Selectable reference frequency Limiter with RSSI generation, operating at 10.7MHz 2nd order low pass data filter with external capacitors Data slicer with self-adjusting threshold
s s s s s s s s s s s
Wireless Components
2-2
Target Specification, October 2001
TDA 5220
preliminary
confidential
Product Description
2.4 Package Outlines
P_TSSOP_28.EPS
Figure 2-1
P-TSSOP-28-1 package outlines
Wireless Components
2-3
Target Specification, October 2001
3
Functional Description
Contents of this Chapter 3.1 3.2 3.3 3.4 Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-2 Pin Definition and Function. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-3 Functional Block Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-9 Functional Blocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-9
TDA 5220
preliminary
confidential
Functional Description
3.1 Pin Configuration
CRST1 VCC LNI TAGC AGND LNO VCC MI M IX AGND FSEL IF O DGND VDD
1 2 3 4 5 6 7 8 9 10 11 12 13 14
28 27 26 25 24 23
CRST2 PDW N PDO DATA 3VO UT THRES FFB OPP SLN SLP L IM X L IM SSEL M SEL
TDA 5220
22 21 20 19 18 17 16 15
Pin_Configuration_5220.wmf
Figure 3-1
IC Pin Configuration
Wireless Components
3-2
Target Specification, October 2001
TDA 5220
preliminary
confidential
Functional Description
3.2 Pin Definition and Function
In the subsequent table the internal circuits connected to the pins of the device are shown. ESD-protection circuits are omitted to ease reading. .
Table 3-1 Pin Definition and Function Pin No. 1 Symbol CRST1 Equivalent I/O-Schematic Function External Crystal Connector 1
4 .1 5 V
1
50uA
2 3
VCC LNI
5V Supply LNA Input
57uA
3
500uA 4k
1k
Wireless Components
3-3
Target Specification, October 2001
TDA 5220
preliminary
confidential
Functional Description
4
TAGC
4.3V
AGC Time Constant Control
3u A 4
1k
1 .4 uA
1 .7V
5 6
AGND LNO
5V
Analogue Ground Return LNA Output
1k
6
7 8
VCC MI
1 .7V
5V Supply Mixer Input
2k
2k
9
MIX
8 9
Complementary Mixer Input
400uA
10
AGND
Analogue Ground Return
Wireless Components
3-4
Target Specification, October 2001
TDA 5220
preliminary
confidential
Functional Description
11
FSEL
868/434 MHz Operating Frequency Selector
7 50 1 .2 V
2k 11
12
IFO
10.7 MHz IF Mixer Output
300uA
2 .2 V
60 12
4 .5 k
13 14 15
DGND VDD MSEL
Digital Ground Return 5V Supply (PLL Counter Circuitry) ASK/FSK Modulation Format Selector
1 .2 V
4 0k 15
16
SSEL
Data-Slicer Reference-Level Selector
1 .2 V
4 0k 16
Wireless Components
3-5
Target Specification, October 2001
TDA 5220
preliminary
confidential
Functional Description
17
LIM
2 .4 V
Limiter Input
15k 17
18
LIMX
33 0 7 5u A
Complementary Limiter Input
18
15k
19
SLP
Data Slicer Positive Input
1 5u A
1 00 19
3k
8 0 A
20
SLN
Data Slicer Negative Input
5u A
10k 20
21
OPP
OpAmp Noninverting Input
5u A
20 0 21
Wireless Components
3-6
Target Specification, October 2001
TDA 5220
preliminary
confidential
Functional Description
22
FFB
Data Filter Feedback Pin
5 uA
1 00 k 22
23
THRES
AGC Threshold Input
5 uA
1 0k 23
24
3VOUT
24 2 0k 3 .1 V
3V Reference Output
25
DATA
Data Output
500 25 40k
Wireless Components
3-7
Target Specification, October 2001
TDA 5220
preliminary
confidential
Functional Description
26
PDO
Peak Detector Output
26 446k
27
PDWN
27
Power Down Input
220k
220k
28
CRST2
External Crystal Connector 2
4 .1 5 V
28
50uA
Wireless Components
3-8
Target Specification, October 2001
TDA 5220
preliminary
confidential
Functional Description
3.3 Functional Block Diagram
VCC
IF Filter
MSEL H=ASK L=FSK
LNO 6
MI 8
MIX 9
IFO 12
LIM 17
LIMX 18 15
FFB 22
OPP 21
SLP 19
SLN 20 Logic + CM 16 SSEL
LNI
RF
3
25
DATA
LNA
+
OP LIMITER FSK PLL Demod
+ CP DATASLICER
TAGC
4
TDA 5220
OTA
:1 :2 VCC 14
VCO
: 64
DET
CRYSTAL OSC
DGND 13 2,7 5,10 11
Loop Filter 1 28
VCC
AGND
FSEL Crystal
Figure 3-2
Main Block Diagram
3.4 Functional Blocks
3.4.1
Low Noise Amplifier (LNA)
The LNA is an on-chip cascode amplifier with a voltage gain of 15 to 20dB. The gain figure is determined by the external matching networks situated ahead of the LNA and between the LNA output LNO (Pin 6) and the Mixer Inputs MI and MIX (Pins 8 and 9). The noise figure of the LNA is approximately 3dB and the current consumption is 500A. The gain can be reduced by approximately 18dB. The switching point of this AGC action can be determined externally by applying a threshold voltage at the THRES pin (Pin 23). This voltage is compared internally with the received signal (RSSI) level generated by the limiter circuitry. In case that the RSSI level is higher than the threshold voltage the LNA gain is reduced and vice versa. The threshold voltage can be generated by attaching a voltage divider between the 3VOUT pin (Pin 24) which provides a temperature stable 3V output generated from the internal bandgap voltage and the THRES pin as described in Section 4.1. The time constant of the AGC action can be determined by connecting a capacitor to the TAGC pin (Pin 4) and should be chosen along with the appropriate threshold voltage according to the
Wireless Components
3-9
Target Specification, October 2001
-
+ FSK - ASK +
PEAK DETECTOR
PDO 26 23 THRES
U REF
AGC Reference
24
3VOUT
Bandgap Reference 27
PDWN
Function_5220.wmf
TDA 5220
preliminary
confidential
Functional Description
intended operating case and interference scenario to be expected during operation. The optimum choice of AGC time constant and the threshold voltage is described in Section 4.1.
3.4.2
Mixer
The Double Balanced Mixer downconverts the input frequency (RF) in the range of 400-440MHz/810-870MHz to the intermediate frequency (IF) at 10.7MHz with a voltage gain of approximately 21dB by utilising either high- or low-side injection of the local oscillator signal. In case the mixer is interfaced only single-ended, the unused mixer input has to be tied to ground via a capacitor. The mixer is followed by a low pass filter with a corner frequency of 20MHz in order to suppress RF signals to appear at the IF output (IFO pin). The IF output is internally consisting of an emitter follower that has a source impedance of approximately 330 = to facilitate interfacing the pin directly to a standard 10.7MHz ceramic filter without additional matching circuitry.
3.4.3
PLL Synthesizer
The Phase Locked Loop synthesiser consists of a VCO, an asynchronous divider chain, a phase detector with charge pump and a loop filter and is fully implemented on-chip. The VCO is including on-chip spiral inductors and varactor diodes. It's nominal centre frequency is 840MHz, the operating range guaranteed over the temperature range specified is 820 to 860MHz. Depending on whether high- or low-side injection of the local oscillator is used the receive frequency ranges are 810 to 840 and 840 to 870MHz or 400 to 420 and 420 to 440MHz (see also Section 4.4). No additional external components are necessary. The oscillator signal is fed both to the synthesiser divider chain and to the downconverting mixer. In case of operation in the 400 to 440 MHz range, the signal is divided by two before it is fed to the mixer. This is controlled by the selection pin FSEL (Pin 11) as described in the following table. The overall division ratio of the divider chain is 64. The loop filter is also realised fully on-chip.
Table 3-2 FSEL Pin Operating States FSEL Open Shorted to ground RF Frequency
400-440 MHz 810-870 MHz
Wireless Components
3 - 10
Target Specification, October 2001
TDA 5220
preliminary
confidential
Functional Description
3.4.4
Crystal Oscillator
The calculation of the value of the necessary quartz load capacitance is shown in Section 4.3, the quartz frequency calculation is explained in Section 4.4.
3.4.5
Limiter
The Limiter is an AC coupled multistage amplifier with a cumulative gain of approximately 80 dB that has a bandpass-characteristic centred around 10.7 MHz. It has a typical input impedance of 330 =to allow for easy interfacing to a 10.7 MHz ceramic IF filter. The limiter circuit also acts as a Receive Signal Strength Indicator (RSSI) generator which produces a DC voltage that is directly proportional to the input signal level as can be seen in Figure 4-2. This signal is used to demodulate ASK-modulated receive signals in the subsequent baseband circuitry. The RSSI output is applied to the modulation format switch, to the Peak Detector input and to the AGC circuitry. In order to demodulate ASK signals the MSEL pin has to in its 'High'-state as described in the next chapter.
3.4.6
FSK Demodulator
To demodulate frequency shift keyed (FSK) signals a PLL circuit is used that is contained fully on chip. The Limiter output differential signal is fed to the linear phase detector as is the output of the 10.7 MHz center frequency VCO. The demodulator gain is typically 180V/kHz. The passive loop filter output that is comprised fully on chip is fed to both the VCO and the modulation format switch described in more detail below. This signal is representing the demodulated signal with high IF-frequencies applied to the demodulator demodulated to logic ones and low IF-frequencies demodulated to logic zeroes. Please note that due to this behaviour a sign inversion of the data occurs in case of high-side injection of the local oscillator at receive frequencies below 840 or 420MHz, respectively. See also . The modulation format switch is actually a switchable amplifier with an AC gain of 11 that is controlled by the MSEL pin (Pin 15) as shown in the following table. This gain was chosen to facilitate detection in the subsequent circuits. The DC gain is 1 in order not to saturate the subsequent Data Filter wih the DC offset produced by the demodulator in case of large frequency offsets of the IF signal. The resulting frequency characteristic and details on the principle of operation of the switch are described in Section 4.6.
Table 3-3 MSEL Pin Operating States MSEL High Low Modulation Format ASK FSK
Wireless Components
3 - 11
Target Specification, October 2001
TDA 5220
preliminary
confidential
Functional Description
The demodulator circuit is switched off in case of reception of ASK signals.
3.4.7
Data Filter
The data filter comprises an OP-Amp with a bandwidth of 100kHz used as a voltage follower and two 100k= on-chip resistors. Along with two external capacitors a 2nd order Sallen-Key low pass filter is formed. The selection of the capacitor values is described in Section 4.2.
3.4.8
Data Slicer
The data slicer is a fast comparator with a bandwidth of 100 kHz. This allows for a maximum receive data rate of up to 100kBaud. The maximum achievable data rate also depends on the IF Filter bandwidth and the local oscillator tolerance values. Both inputs are accessible. The output delivers a digital data signal (CMOS-like levels) for subsequent circuits. A self-adjusting slicer-threshold on pin 20 its generated by a RC-term. In ASK-mode alternatively a scaled value of the voltage at the PDO-output (approx. 87%) can be used as the slicerthreshold. The data slicer threshold generation alternatives are described in more detail in Section 4.5.
3.4.9
Peak Detector
The peak detector generates a DC voltage which is proportional to the peak value of the receive data signal. A capacitor is necessary. The input is connected to the output of the RSSI-output of the Limiter, the output is connected to the PDO pin (Pin 26). This output can be used as an indicator for the received signal strength to use in wake-up circuits and as a reference for the data slicer in ASK mode. Note that the RSSI level is also output in case of FSK mode.
3.4.10
Bandgap Reference Circuitry
A Bandgap Reference Circuit provides a temperature stable reference voltage for the device. A power down mode is available to switch off all subcircuits which is controlled by the PWDN pin (Pin 27) as shown in the following table. The supply current drawn in this case is typically 50nA.
Table 3-4 PDWN Pin Operating States PDWN Open or tied to ground Tied to Vs Operating State Powerdown Mode Receiver On
Wireless Components
3 - 12
Target Specification, October 2001
4
Applications
Contents of this Chapter 4.1 4.2 4.3 4.4 4.5 4.6 4.7 Choice of LNA Threshold Voltage and Time Constant . . . . . . . . . . . . 4-2 Data Filter Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-4 Quartz Load Capacitance Calculation . . . . . . . . . . . . . . . . . . . . . . . . 4-5 Quartz Frequency Calculation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-6 Data Slicer Threshold Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-7 ASK/FSK Switch Functional Description . . . . . . . . . . . . . . . . . . . . . . 4-8 Principle of the Precharge Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-11
TDA 5220
preliminary
confidential
Applications
4.1 Choice of LNA Threshold Voltage and Time Constant
In the following figure the internal circuitry of the LNA automatic gain control is shown.
R1
R2
Uth re s h old Pins: 24 23
20k
RSSI (0.8 - 2.8V)
OTA +3.1 V
VCC
Ilo a d RSSI > Uth r es h o ld : Ilo a d =4.2A RSSI < Uth r es h o ld : Ilo a d = -1.5A 4 UC C Gain control voltage
LNA
Uc :< 2.6V : Gain high Uc :> 2.6V : Gain low Uc ma x = VC C - 0.7V Uc min = 1.67V
LNA_autom.wmf
Figure 4-1
LNA Automatic Gain Control Circuitry
The LNA automatic gain control circuitry consists of an operational transimpedance amplifier that is used to compare the received signal strength signal (RSSI) generated by the Limiter with an externally provided threshold voltage Uthres. As shown in the following figure the threshold voltage can have any value between approximately 0.8 and 2.8V to provide a switching point within the receive signal dynamic range. This voltage Uthres is applied to the THRES pin (Pin 23) The threshold voltage can be generated by attaching a voltage divider between the 3VOUT pin (Pin 24) which provides a temperature stable 3V output generated from the internal bandgap voltage and the THRES pin. If the RSSI level generated by the Limiter is higher than Uthres, the OTA generates a positive current Iload. This yields a voltage rise on the TAGC pin (Pin 4). Otherwise, the OTA generates a negative current. These currents do not have the same values in order to achieve a fast-attack and slow-release action of the AGC and are used to charge an external capacitor which finally generates the LNA gain control voltage.
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TDA 5220
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Applications
LNA always in high gain mode
3
2.5
UTHRES Voltage Range
2
RSSI Level Range
RSSI Level
1.5
1
LNA always in low gain mode
0.5
0 -120
-110
-100
-90
-80
-70
-60
-50
-40
-30
Input Level at LNA Input [dBm]
RSSI-AGC.wmf
Figure 4-2
RSSI Level and Permissive AGC Threshold Levels
The switching point should be chosen according to the intended operating scenario. The determination of the optimum point is described in the accompanying Application Note, a threshold voltage level of 1.8V is apparently a viable choice. It should be noted that the output of the 3VOUT pin is capable of driving up to 50A, but that the THRES pin input current is only in the region of 40nA. As the current drawn out of the 3VOUT pin is directly related to the receiver power consumption, the power divider resistors should have high impedance values. The sum of R1 and R2 has to be 600k in order to yield 3V at the 3VOUT pin. R1 can thus be chosen as 240k, R2 as 360k to yield an overall 3VOUT output current of 5A1 and a threshold voltage of 1.8V Note: If the LNA gain shall be kept in either high or low gain mode this has to be accomplished by tying the THRES pin to a fixed voltage. In order to achieve high gain mode operation, a voltage higher than 2.8V shall be applied to the THRES pin, such as a short to the 3VOLT pin. In order to achieve low gain mode operation a voltage lower than 0.7V shall be applied to the THRES, such as a short to ground. As stated above the capacitor connected to the TAGC pin is generating the gain control voltage of the LNA due to the charging and discharging currents of the OTA and thus is also responsible for the AGC time constant. As the charging and discharging currents are not equal two different time constants will result. The time constant corresponding to the charging process of the capacitor shall be chosen according to the data rate. According to measurements performed at Infineon the capacitor value should be greater than 47nF.
1. note the 20k resistor in series with the 3.1V internal voltage source
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TDA 5220
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Applications
4.2 Data Filter Design
Utilising the on-board voltage follower and the two 100k on-chip resistors a 2nd order Sallen-Key low pass data filter can be constructed by adding 2 external capacitors between pins 19 (SLP) and 22 (FFB) and to pin 21 (OPP) as depicted in the following figure and described in the following formulas1.
C1
C2
Pins: R 100k
22 R 100k
21
19
Filter_Design.wmf
Figure 4-3
Data Filter Design
(1)(2)
2Q b C1 = ---------------------R2f 3dB
with
bC2 = -------------------------4QRf 3dB
b Q = -----a
where
(3)the quality factor of the poles
in case of a Bessel filter a = 1.3617, b = 0.618 and thus Q = 0.577
and in case of a Butterworth filter a = 1.414, b = 1 and thus Q = 0.71
Example: Butterworth filter with f3dB = 5kHz and R = 100k: C1 = 450pF, C2 = 225pF
1. taken from Tietze/Schenk: Halbleiterschaltungstechnik, Springer Berlin, 1999
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Target Specification, October 2001
TDA 5220
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Applications
4.3 Quartz Load Capacitance Calculation
The value of the capacitor necessary to achieve that the quartz oscillator is operating at the intended frequency is determined by the reactive part of the negative resistance of the oscillator circuit as shown in Section 5.1.3 and by the quartz specifications given by the quartz manufacturer.
CS Pin 28 Crystal Input impedance Z1-28
TDA5220
Pin 1
Quartz_load.wmf
Figure 4-4
Determination of Series Capacitance Value for the Quartz Oscillator
Crystal specified with load capacitance
CS =
1 1 + 2 f X L Cl
with Cl the load capacitance (refer to the quartz crystal specification). Example: 13.4 MHz: CL = 12 pFXL=1010 CS = 5.9 pF This value may be obtained in high accuracy by putting two capacitors in series to the quartz, such as 22pF and 8.2pF for 13.4MHz.
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Applications
4.4 Quartz Frequency Calculation
As described in Section 3.4.3 the operating range of the on-chip VCO is 820 to 860 MHz with a nominal center frequency of 840MHz. This signal is divided by 2 before applied to the mixer in case of operation at 434 MHz. This local oscillator signal can be used to downconvert the RF signals both with high- or lowside injection at the mixer. The resulting receive frequency ranges then extend between 810 and 870MHz or between 400 and 440MHz. Low-side injection of the local oscillator has to be used for receive frequencies between 840 and 870MHz as well as high-side injection for receive frequencies below 840MHz. Corresponding to that in the 400MHz region low-side injection is applicable for receive frequencies above 420MHz, high-side injection below this frequency. Therefore for operation both in the 868 and the 434 MHz ISM bands low-side injection of the local oscillator has to be used. Then the local oscillator frequency is calculated by subtracting the IF frequency (10.7 MHz) from the RF frequency (434 or 868 MHz). Please note that no sign-inversion occurs in case of reception and demodulation of FSK-modulated signals. The overall division ratios in the PLL is 64 in case of operation at 868 MHz or 32 in case of operation at 434 MHz. The quartz frequency in case of low-side injection may be calculated by using the following formula:
QU = (RF - 10.7) / r with RF LO QU r receive frequency local oscillator (PLL) frequency (RF - 10.7) quartz oscillator frequency ratio of local oscillator (PLL) frequency and quartz frequency as shown in the subsequent table
Table 4-1 Dependence of PLL Overall Division Ratio on FSEL FSEL open GND Ratio r = (fLO/fQU)
32 64
:
f QU = (868.4 MHz - 10.7 MHz ) / 64 = 13.40156 MHz f QU = (434.2 MHz - 10.7 MHz ) / 32 = 13.23437 MHz
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Applications
4.5 Data Slicer Threshold Generation
The threshold of the data slicer can be generated using an external R-C integrator as shown in Figure 4-5. The cut-off frequency of the R-C integrator has to be lower than the lowest frequency appearing in the data signal. In order to keep distortion low, the minimum value for R is 20k.
R C
Pins:
19
20 Uthreshold
data out 25
data filter
CM data slicer
Data_slice1.wmf
Figure 4-5
Data Slicer Threshold Generation with External R-C Integrator
In case of ASK operation another possibility for threshold generation is to use the peak detector in connection with an internal resistive divider and one capacitor as shown in the following figure. The component values are depending on the coding scheme and the protocol used.
C data out Pins: peak detector 56k 390k data slicer Uthreshold data filter CP 26 25
Data_slice2.wmf
Figure 4-6
Data Slicer Threshold Generation Utilising the Peak Detector
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4.6 ASK/FSK Switch Functional Description
The TDA5220 is containing an ASK/FSK switch which can be controlled via Pin 15 (MSEL). This switch is actually consisting of 2 operational amplifiers that are having a gain of 1 in case of the ASK amplifier and a gain of 11 in case of the FSK amplifier in order to achieve an appropriate demodulation gain characteristic. In order to compensate for the DC-offset generated especially in case of the FSK PLL demodulator there is a feedback connection between the threshold voltage of the bit slicer comparator (Pin 20) to the negative input of the FSK switch amplifier. In ASK-mode alternatively to the voltage at Pin 20 (SLN) a value of approx. 87% of the peak-detector output-voltage at Pin 26 (PDO) can be used as the slicerreference level. The selection between these modes is controlled by Pin 16 (SSEL). This is shown in the following figure.
MSEL 15 H=ASK L=FSK from RSSI Gen (ASK signal) ASK/FSK Switch
PEAK DETECTOR
PDO 26
R=56k C=100 nF R=390k Data Filter Comp + CP + CM H=CP L=CM
FSK PLL Demodulator
+
R1=100k
R2=100k v=1
ASK + FSK -
25
DATA Out
0.18 mV/kHz
AC
R3=300k typ. 2 V 1.5 V......2.5 V
DC
R4=30k ASK mode: v=1 FSK mode: v=11 22 FFB 21 OOP 19 SLP 20 SLN 16 SSEL
C1 C2
R C
1
ask_fsk_datapath.WMF
Figure 4-7
ASK/FSK mode datapath
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Target Specification, October 2001
TDA 5220
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Applications
4.6.1
FSK Mode
The FSK datapath has a bandpass characterisitc due to the feedback shown above (highpass) and the data filter (lowpass). The lower cutoff frequency f2 is determined by the external RC-combination. The upper cutoff frequency f3 is determined by the data filter bandwidth. The demodulation gain of the FSK PLL demodulator is 180V/kHz. This gain is increased by the gain v of the FSK switch, which is 11. Therefore the resulting dynamic gain of this circuit is 2mV/kHz within the bandpass. The gain for the DC content of FSK signal remains at 180V/kHz. The cutoff frequencies of the bandpass have to be chosen such that the spectrum of the data signal is influenced in an acceptable amount. In case that the user data is containing long sequences of logical zeroes the effect of the drift-off of the bit slicer threshold voltage can be lowered if the offset voltage inherent at the negative input of the slicer comparator (Pin20) is used. The comparator has no hysteresis built in. This offset voltage is generated by the bias current of the negative input of the comparator (i.e. 20nA) running over the external resistor R. This voltage raises the voltage appearing at pin 20 (e.g. 1mV with R = 100k). In order to obtain benefit of this asymmetrical offset for the demodulation of long zeros the lower of the two FSK frequencies should be chosen in the transmitter as the zerosymbol frequency. In the following figure the shape of the above mentioned bandpass is shown.
gain (pin19)
v v -3dB
20dB/dec
-40dB/dec
3dB 0dB f DC f1 f2 f3
0.18m Hz V/k
2m Hz V/k
frequenzgang.WMF
Figure 4-8
Frequency characterstic in case of FSK mode
The cutoff frequencies are calculated with the following formulas:
f1 =
1 R 330k C 2 R + 330k
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f 2 = v f1 = 11 f1
f 3 = f 3dB
f3 is the 3dB cutoff frequency of the data filter - see Section 4.2. Example: R = 100k,=C = 47nF This leads tof1 = 44Hz and f2 = 485Hz
4.6.2
ASK Mode
In case the receiver is operated in ASK mode the datapath frequency charactersitic is dominated by the data filter alone, thus it is lowpass shaped.The cutoff frequency is determined by the external capacitors C12 and C14 and the internal 100k resistors as described in Section 4.2
0dB -3dB
-40dB/dec
f f3dB
freq_ask.WMF
Figure 4-9
Frequency charcteristic in case of ASK mode
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Target Specification, October 2001
TDA 5220
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Applications
4.7 Principle of the Precharge Circuit
In case the data slicer threshold shall be generated with an external RC network as described in Section 4.5 it is necessary to use large values for the capacitor C attached to the SLN pin (pin 20) in order to achieve long time constants. This results also from the fact that the choice of the value for R connected between the SLP and SLN pins (pins 19 and 20) is limited by the 330k resistor appearing in parallel to R as can be seen in Figure 4-7. Apart from this a resistor value of 100k leads to a voltage offset of 1mv at the comparator input as described in Section 4.6.1. The resulting startup time constant 1 can be calculated with:
1 = (R // 330k) * C
In case R is chosen to be 100k and C is chosen as 47nF this leads to
1 = (100k // 330k) * 47nF = 77k * 47nF = 3.6ms
When the device is turned on this time constant dominates the time necessary for the device to be able to demodulate data properly. In the powerdown mode the capacitor is only discharged by leakage currents. In order to reduce the turn-on time in the presence of large values of C a precharge circuit was included in the TDA5220 as shown in the following figure.
C2
R1+R2=600k R1 R2 C R Uth r es h o ld 24 23 Uc>Us U2 0 / 240uA OTA 20k +3.1V +2.4V Uc+ Us
U2<2.4V : I=240uA U2>2.4V : I=0
Figure 4-10
Principle of the precharge circuit
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+
precharge.WMF
Target Specification, October 2001
TDA 5220
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Applications
This circuit charges the capacitor C with an inrush current Iload of typically 220A for a duration of T2 until the voltage Uc appearing on the capacitor is equal to the voltage Us at the input of the data filter. This voltage is limited to 2.5V. As soon as these voltages are equal or the duration T2 is exceeded the precharge circuit is disabled.
2 is the time constant of the charging process of C which can be calculated as 2 =20k * C2
as the sum of R1 and R2 is sufficiently large and thus can be neglected. T2 can then be calculated according to the following formula:
ae o c 1 2 1 . 6 T 2 = 2 ln c c 1 - 2 . 4V c 3V e
The voltage transient during the charging of C2 is shown in the following figure:
U2
3V 2.4V
2
T2
e-fkt1.WMF
Figure 4-11
Voltage appearing on C2 during precharging process
The voltage appearing on the capacitor C connected to pin 20 is shown in the following figure. It can be seen that due to the fact that it is charged by a constant current source it exhibits a linear increase in voltage which is limited to USmax = 2.5V which is also the approximate operating point of the data filter input. The time constant appearing in this case can be denoted as T3, which can be calculated with
USmax C 2,5V T3 = ----------------------- = ---------------- C 220A 220A
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Applications
Uc
Us
T3
e-Fkt2.WMF
Figure 4-12
Voltage transient on capacitor C attached to pin 20
As an example the choice of C2 = 22nF and C = 47nF yields
2 = 0.44ms
T2 = 0.71ms T3 = 0.53ms This means that in this case the inrush current could flow for a duration of 0.64ms but stops already after 0.49ms when the USmax limit has been reached. T3 should always be chosen to be shorter than T2. It has to be noted finally that during the turn-on duration T2 the overall device power consumption is increased by the 220A needed to charge C. The precharge circuit may be disabled if C2 is not equipped. This yields a T2 close to zero. Note that the sum of R4 and R5 has to be 600k in order to produce 3V at the THRES pin as this voltage is internally used also as the reference for the FSK demodulator.
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Target Specification, October 2001
5
Reference
Contents of this Chapter 5.1 Electrical Data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-2
TDA 5220
preliminary
confidential
Reference
5.1 Electrical Data
5.1.1
Absolute Maximum Ratings
WARNING
The maximum ratings may not be exceeded under any circumstances, not even momentarily and individually, as permanent damage to the IC will result.
Table 5-1 Absolute Maximum Ratings, Ambient temperature TAMB=-40C ... + 105C # Parameter Symbol Limit Values min 1 2 3 4 5 Supply Voltage Junction Temperature Storage Temperature Thermal Resistance ESD integrity, all pins excl. Pins 1,3, 6, 28 ESD integrity Pins 1,3,6,28 Vs Tj Ts RthJA VESD -0.3 -40 -40 max 5.5 +150 +125 114 +2 +1.5 V C C K/W kV kV HBM according to MIL STD 883D, method 3015.7 Unit Remarks
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5.1.2
Operating Range
Within the operational range the IC operates as explained in the circuit description. The AC/DC characteristic limits are not guaranteed. Currents flowing into the device are denoted as positive currents and v.v.
Supply voltage: VCC = 4.5V .. 5.5V
Table 5-2 Operating Range, Ambient temperature TAMB= -40C ... + 105C # Parameter Symbol Limit Values min 1 Supply Current ISF 868 ISF 434 ISA 868 ISA 434 RFin t.b.d. t.b.d. t.b.d. t.b.d. -106 -100 max t.b.d. t.b.d. t.b.d. t.b.d. -13 -13 mA mA mA mA dBm dBm fRF = 868MHz, FSK Mode fRF = 434MHz, FSK Mode fRF = 868MHz, ASK Mode fRF = 434MHz, ASK Mode @ source impedance 50, BER 2E-3, average power level, Manchester encoded datarate 4kBit, 280kHz IF Bandwidth
s
Unit
Test Conditions
L
Item
2
Receiver Input Level ASK FSK, frequ. dev. 50kHz
3 4 5
LNI Input Frequency MI/MIX Input Frequency 3dB IF Frequency Range ASK FSK
fRF fMI
400/ 810 400/ 810 5 10.4
440/ 870 440/ 870 23 11
MHz MHz
fIF -3dB
MHz
s
s This value is guaranteed by design.
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Target Specification, October 2001
TDA 5220
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Reference
5.1.3
AC/DC Characteristics at TAMB = 25C
AC/DC characteristics involve the spread of values guaranteed within the specified voltage and ambient temperature range. Typical characteristics are the median of the production. Currents flowing into the device are denoted as positive currents and vice versa.
Table 5-3 AC/DC Characteristics with TA 25 C, VVCC = 4.5 ... 5.5 V Parameter Symbol min Supply Supply Current 1 2 Supply current, standby mode Supply current, device operating in 868 MHz range, FSK mode Supply current, device operating in 434 MHz range, FSK mode Supply current, device operating in 868 MHz range, ASK mode Supply current, device operating in 434 MHz range, ASK mode IS PDWN ISF 868 t.b.d. 50 5.9 t.b.d. t.b.d. nA mA Pin 27 (PDWN) open or tied to 0 V Pin 11 (FSEL) tied to GND, Pin 15 (MSEL) tied to GND Pin 11 (FSEL) open, Pin 15 (MSEL) tied to GND Pin 11 (FSEL) tied to GND, Pin 15 (MSEL) open Pin 11 (FSEL) open, Pin 15 (MSEL) open Limit Values typ max Unit Test Conditions L Item
3
ISF 434
t.b.d.
5.7
t.b.d.
mA
4
ISA 868
t.b.d.
5.2
t.b.d.
mA
5
ISA 434
t.b.d.
5
t.b.d.
mA
LNA Signal Input LNI (PIN 3), VTHRES > 2.8V, high gain mode 1 Average Power Level at BER = 2E-3 (Sensitivity) ASK Average Power Level at BER = 2E-3 (Sensitivity) FSK Input impedance, fRF=434 MHz Input impedance, fRF=869 MHz Input level @ 1dB compression Input 3rd order intercept point fRF=434 MHz Input 3rd order intercept point fRF=869 MHz RFin -110 dBm Manchester encoded datarate 4kBit, 280kHz IF Bandwidth Manchester enc. datarate 4kBit, 280kHz IF Bandw., 50kHz pk. dev.
s
2
RFin
-103
dBm
s
3 4 5 6
S11 LNA S11 LNA P1dBLNA IIP3LNA IIP3LNA
0.873 / -34.7 deg 0.738 / -73.5 deg -15 -10 dBm dBm matched input
s
s
s s
7
-14
dBm
matched input
s
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Target Specification, October 2001
TDA 5220
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Reference
Table 5-3 AC/DC Characteristics with TA 25 C, VVCC = 4.5 ... 5.5 V (continued) Parameter Symbol min 8 LO signal feedthrough at antenna port LOLNI Limit Values typ max -73 dBm
s
Unit
Test Conditions
L
Item
Signal Output LNO (PIN 6), VTHRES > 2.8V, high gain mode 1 2 3 4 5 6 Gain fRF=434 MHz Gain fRF=869 MHz Output impedance, fRF=434 MHz Output impedance, fRF=869 MHz Voltage Gain Antenna to IFO fRF=434 MHz Voltage Gain Antenna to IFO fRF=869 MHz S21 LNA S21 LNA S22 LNA S22 LNA GAntMI GAntMI 1.509 / 138.2 deg 1.419 / 101.7 deg 0.886 / -12.9 deg 0.866 / -24.2 deg 42 40 dB dB
s s s
s
Signal Input LNI, VTHRES = GND, low gain mode 1 2 3 4 5 Input impedance, fRF=434 MHz Input impedance, fRF=869 MHz Input level @ 1dB C. P fRF = 434 MHz Input level @ 1dB C. P fRF = 869 MHz Input 3rd order intercept point fRF=434 MHz Input 3rd order intercept point fRF=869 MHz S11 LNA S11 LNA P1dBLNA P1dBLNA IIP3LNA IIP3LNA 0.873 / -34.7 deg 0.738 / -73.5 deg -18 -6 -10 dBm dBm dBm matched input matched input matched input
s
s
s
s
s
6
-5
dBm
matched input
s
Signal Output LNO, VTHRES = GND, low gain mode 1 2 3 4 5 6 Gain fRF=434 MHz Gain fRF=869 MHz Output impedance, fRF=434 MHz Output impedance, fRF=869 MHz Voltage Gain Antenna to MI fRF=434 MHz Voltage Gain Antenna to MI fRF=869 MHz S21 LNA S21 LNA S22 LNA S22 LNA GAntMI GAntMI 0.183 / 140.6 deg 0.179 / 109.1deg 0.897 / -13.6 deg 0.868 / -26.3 deg 22 19 dB dB
s s s
s
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Target Specification, October 2001
TDA 5220
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Reference
Table 5-3 AC/DC Characteristics with TA 25 C, VVCC = 4.5 ... 5.5 V (continued) Parameter Symbol min Signal 3VOUT (PIN 24) 1 2 Output voltage Current out V3VOUT I3VOUT 2.9 -3 3.1 -5 3.3 -10 V A 3VOUT Pin open see Section 4.1 Limit Values typ max Unit Test Conditions L Item
Signal THRES (PIN 23) 1 2 3 4 Input Voltage range LNA low gain mode LNA high gain mode Current in VTHRES VTHRES VTHRES ITHRES_in 0 0 2.8 3 5 VS VS-1V V V V nA or shorted to Pin 24 see Section 4.1
Signal TAGC (PIN 4) 1 2 Current out, LNA low gain state Current in, LNA high gain state ITAGC_out VTAGC_in -3.6 1 -4.2 1.6 -5 2.2 A A RSSI > VTHRES RSSI>VTHRES
MIXER Signal Input MI/MIX (PINS 8/9) 1 2 3 Input impedance, fRF=434 MHz Input impedance, fRF=869 MHz Input 3rd order intercept point fRF=434 MHz Input 3rd order intercept point fRF=869 MHz S11 MIX S11 MIX IIP3MIX IIP3MIX 0.942 / -14.4 deg 0.918 / -28.1 deg -28 dBm
s
s
s
4
-26
dBm
s
Signal Output IFO (PIN 12) 1 2 3 Output impedance Conversion Voltage Gain fRF=434 MHz Conversion Voltage Gain fRF=869 MHz ZIFO GMIX GMIX 330 +19 +18 dB dB
s
LIMITER Signal Input LIM/LIMX (PINS 17/18) 1 2 3 4 Input Impedance RSSI dynamic range RSSI linearity Operating frequency (3dB points) ZLIM DRRSSI LINRSSI fLIM 5 264 60 330 396 80 dB dB 23 MHz
s s s
1
10.7
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Target Specification, October 2001
TDA 5220
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Reference
Table 5-3 AC/DC Characteristics with TA 25 C, VVCC = 4.5 ... 5.5 V (continued) Parameter Symbol min DATA FILTER 1 2 Useable bandwidth RSSI Level at Data Filter Output SLP, RFIN=-103dBm RSSI Level at Data Filter Output SLP, RFIN=-30dBm BWBB FILT RSSIlow 0.3 100 1 kHz V LNA in high gain mode LNA in high gain mode
s
Limit Values typ max
Unit
Test Conditions
L
Item
3
RSSIhigh
1.8
3
V
Slicer, Signal Output DATA (PIN 25) 1 2 3 Maximum Datarate LOW output voltage HIGH output voltage DRmax VSLIC_L VSLIC_H 0 VS1.3V VS-1V 100 0.1 VS0.7V kBps V V NRZ, 20pF capacitive loading
s
Slicer, Negative Input (PIN 20) 1 Precharge Current Out IPCH_SLN -100 -220 -300 A see Section 4.7
PEAK DETECTOR Signal Output PDO (PIN 26) 1 2 Load current Internal resistive load Iload R -600 t.b.d. -950 446 -1300 t.b.d. A k
CRYSTAL OSCILLATOR Signals CRSTL1, CRSTL 2, (PINS 1/28) 1 2 3 Operating frequency Input Impedance @ ~13MHz Serial Capacity @ ~13MHz fCRSTL Z1-28 CS13=C1 t.b.d. -600 +j1010 5.9 14 MHz pF fundamental mode, series resonance
s
ASK/FSK Signal Switch Signal MSEL (PIN 15) 1 2 3 ASK Mode FSK Mode Input bias current MSEL VMSEL VMSEL IMSEL 1.4 0 t.b.d. -11 4 0.2 t.b.d. V V A MSEL tied to GND or open
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Target Specification, October 2001
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Reference
Table 5-3 AC/DC Characteristics with TA 25 C, VVCC = 4.5 ... 5.5 V (continued) Parameter Symbol min FSK DEMODULATOR 1 2 Demodulation Gain Useable IF Bandwidth GFMDEM BWIFPLL 85 10.2 180 10.7 225 11.2 V/ kHz MHz Limit Values typ max Unit Test Conditions L Item
POWER DOWN MODE Signal PDWN (PIN 27) 1 2 3 4 Powerdown Mode On Powerdown Mode Off Input bias current PDWN Start-up Time until valid signal is detected at IF PWDNON PWDNOff IPDWN TSU 0 2.8 19 1 0.8 VS V V uA ms Power On Mode
VCO MULTIPLEXER Signal FSEL (PIN 11) 1 2 3 fRF range 434 MHz fRF range 869 MHz Input bias current FSEL VFSEL VFSEL IFSEL 1.4 0 -160 -200 4 0.2 -240 V V A FSEL tied to GND or open
DATA-SLICER REFERENCE-LEVEL Signal SSEL (PIN 16), ASK-Mode 1 2 Slicer-Reference is voltage at Pin 20 (SLN) Slicer-Reference is approx. 87% of the voltage at Pin 26 (PDO) Input bias current SSEL VSSEL VSSEL 1.4 0 4 0.2 V V or open
3
ISSEL
-3
-5
-7
A
SSEL tied to GND
s Measured only in lab.
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Target Specification, October 2001
TDA 5220
preliminary
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Reference
5.1.4
AC/DC Characteristics at TAMB = -40 to 105C
Currents flowing into the device are denoted as positive currents and vice versa
Table 5-4 AC/DC Characteristics with TAMB= -40C ... + 105C, VVCC = 4.5 ... 5.5 V Parameter Symbol min Supply Supply Current 1 2 Supply current, standby mode Supply current, device operating in 868 MHz range, FSK mode Supply current, device operating in 434 MHz range, FSK mode Supply current, device operating in 868 MHz range, ASK mode Supply current, device operating in 434 MHz range, ASK mode IS PDWN ISF 868 t.b.d. 50 5.9 t.b.d. t.b.d. nA mA Pin 27 (PDWN) open or tied to 0 V Pin 11 (FSEL) tied to GND, Pin 15 (MSEL) tied to GND Pin 11 (FSEL) open, Pin 15 (MSEL) tied to GND Pin 11 (FSEL) tied to GND, Pin 15 (MSEL) open Pin 11 (FSEL) open, Pin 15 (MSEL) open Limit Values typ max Unit Test Conditions L Item
3
ISF 434
t.b.d.
5.7
t.b.d.
mA
4
ISA 868
t.b.d.
5.2
t.b.d.
mA
5
ISA 434
t.b.d.
5
t.b.d.
mA
Signal 3VOUT (PIN 24) 1 2 Output voltage Current out V3VOUT I3VOUT 2.9 -3 3.1 -5 3.3 -10 V A 3VOUT Pin open see Section 4.1
Signal THRES (PIN 23) 1 2 3 4 Input Voltage range LNA low gain mode LNA high gain mode Current in VTHRES VTHRES VTHRES ITHRES_in 0 0 3 5 VS-1V 0.3 VS V V V nA or shorted to Pin 24 see Section 4.1
Signal TAGC (PIN 4) 1 2 Current out, LNA low gain state Current in, LNA high gain state ITAGC_out VTAGC_in -1 0.5 -4.2 1.5 -8 5 A A RSSI > VTHRES RSSI>VTHRES
MIXER 1 2 Conversion Voltage Gain fRF=434 MHz Conversion Voltage Gain fRF=869 MHz GMIX GMIX +19 +18 dB dB
LIMITER Signal Input LIM/LIMX (PINS 17/18) 1 RSSI dynamic range DRRSSI 60 80 dB
Wireless Components
5-9
Target Specification, October 2001
TDA 5220
preliminary
confidential
Reference
Table 5-4 AC/DC Characteristics with TAMB= -40C ... + 105C, VVCC = 4.5 ... 5.5 V Parameter Symbol min DATA FILTER 2 RSSI Level at Data Filter Output SLP, RFIN=-103dBm RSSI Level at Data Filter Output SLP, RFIN=-30dBm RSSIlow 0.3 1 V LNA in high gain mode LNA in high gain mode Limit Values typ max Unit Test Conditions L Item
3
RSSIhigh
1.8
3
V
Slicer, Signal Output DATA (PIN 25) 1 2 3 Maximum Datarate LOW output voltage HIGH output voltage DRmax VSLIC_L VSLIC_H 0 VS1.5V VS-1V 100 0.1 VS0.5V kBps V V NRZ, 20pF capacitive loading
s
Slicer, Negative Input (PIN 20) 1 Precharge Current Out IPCH_SLN -100 -220 -300 A see Section 4.7
PEAK DETECTOR Signal Output PDO (PIN 26) 1 2 Load current Internal resistive load Iload R -400 t.b.d. -850 446 -1400 t.b.d. A k
CRYSTAL OSCILLATOR Signals CRSTL1, CRSTL 2, (PINS 1/28) 1 Operating frequency fCRSTL t.b.d. 14 MHz fundamental mode, series resonance
ASK/FSK Signal Switch Signal MSEL (PIN 15) 1 2 3 ASK Mode FSK Mode Input bias current MSEL VMSEL VMSEL IMSEL 1.4 0 t.b.d. -11 4 0.2 t.b.d. V V A MSEL tied to GND or open
FSK DEMODULATOR 1 2 Demodulation Gain Useable IF Bandwidth GFMDEM BWIFPLL 105 10.2 180 10.7 245 11.2 V/ kHz MHz
POWER DOWN MODE Signal PDWN (PIN 27) 1 2 Powerdown Mode On Powerdown Mode Off PWDNON PWDNOff 0 2.8 0.8 VS V V
Wireless Components
5 - 10
Target Specification, October 2001
TDA 5220
preliminary
confidential
Reference
Table 5-4 AC/DC Characteristics with TAMB= -40C ... + 105C, VVCC = 4.5 ... 5.5 V Parameter Symbol min 3 Start-up Time until valid signal is detected at IF TSU Limit Values typ max 1 ms Unit Test Conditions L Item
VCO MULTIPLEXER Signal FSEL (PIN 11) 1 2 3 fRF range 434 MHz fRF range 869 MHz Input bias current FSEL VFSEL VFSEL IFSEL 1.4 0 -110 -200 4 0.2 -340 V V A FSEL tied to GND or open
DATA-SLICER REFERENCE-LEVEL Signal SSEL (PIN 16), ASK-Mode 1 2 Slicer-Reference is voltage at Pin 20 (SLN) Slicer-Reference is approx. 87% of the voltage at Pin 26 (PDO) Input bias current SSEL VSSEL VSSEL 1.4 0 4 0.2 V V or open
3
ISSEL
t.b.d.
-11
t.b.d.
A
SSEL tied to GND
Wireless Components
5 - 11
Target Specification, October 2001

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